1. Field of the Invention
The present invention relates to a system for simultaneously determining the memory test result of semiconductor memory devices configured such that data recorded thereto is read again, and more particularly, to a system for simultaneously determining a memory test result, wherein when two or more memory devices as devices under test (DUTs) are placed in physically different positions, they may be simultaneously tested, regardless of the input time difference of the read data depending on the physical distance.
2. Description of the Related Art
Regarding semiconductor test devices, a plurality of patents including Korean Patent Application Publication No. 10-2009-0127689 (hereinafter referred to as “cited reference”) has been applied and laid-open.
In this cited reference, the memory test device includes a general register for calculation using a predetermined general command; an extension register having a capacity greater than that of the general register and for calculation using a predetermined extension command; and a controller for writing a predetermined test pattern to an external memory using the extension command, reading the test pattern written to the memory, determining whether the written test pattern and the read test pattern are matched with each other, and determining whether the memory is faulty or not using the general command.
In conventional semiconductor test devices including cited reference, a memory device (DUT) is electrically coupled with a pattern generator for testing thereof.
FIG. 1 illustrates a typical structure for a memory burn-in test, including a pattern generator 1 for testing a memory device (DUT), a feed through board 3 for transmitting a signal, and a burn-in board 6 for testing.
Upon recording for a memory test in such a structure, a signal is output from the pattern generator 1 and then recorded in the sequence of from a closest memory device 4 that is disposed closer to the pattern generator to a last memory device 5 that is disposed farther from the pattern generator, among memory devices mounted on the burn-in board 6.
On the other hand, in order to determine whether the read data is matched with the recorded data, the data is sequentially read from the closest memory device 4 to the last memory device 5 and thus whether it is normal or not is checked.
In this procedure, because the closest memory device 4 and the last memory device 5 are physically distant from each other, a difference in data input time is created and becomes apparent upon reading of the data.
FIG. 2 schematically illustrates the electrical connection thereof.
As illustrated in FIG. 2, an address line and a command line 7 are connected with a common line, and a data line 8 is connected so as to be commonly electrically conductive. As such, chip selection (CS) pins are separately connected, so that the closest memory device 4 that is disposed closer and the farthest memory device 5 that is disposed farther allow for an individual reading function.
Specifically, a command is sequentially applied to the memory devices 4, 5 as seen in FIG. 2, and then read in the applied sequence, thus obtaining data. In this procedure, because the closest memory device 4 and the farthest memory device 5 are physically distant from each other, the data arrival time may be different. As such, this structure includes a single data path connected between the closest memory device 4 and the farthest memory device 5, and thus a single determination clock (a strobe clock) may be applied. Moreover, to overcome the time difference, a strobe clock as the determination clock is adjusted so as to be variable for a predetermined period of time.